View LTC6090-5-15_8307518.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltc6090 typical a pplica t ion fea t ures descrip t ion 140v cmos rail-to-rail output, picoamp input current op amp the lt c ? 6090/ltc6090-5 are high voltage, precision monolithic operational amplifiers. the ltc6090 is unity gain stable. the ltc6090-5 is stable in noise gain con - figurations of 5 or greater. both amplifiers feature high open loop gain, low input referred offset voltage and noise, and pa input bias current and are ideal for high voltage, high impedance buffering and/ or high gain configurations. the amplifiers are internally protected against over - temperature conditions. a thermal warning output, tflag, goes active when the die temperature approaches 150c. the output stage may be turned off with the output disable pin od . by tying the od pin to the thermal warning output (tflag ), the part will disable the output stage when it is out of the safe operating area. these pins easily interface to any logic family. both amplifiers may be run from a single 140 v or spit 70v power supplies and are capable of driving up to 200pf of load capacitance. they are available in either an 8-lead so or 16- lead tssop package with exposed pad for low thermal resistance. 140v p-p sine wave output a pplica t ions n supply range: 4.75v to 70v (140v) n 0.1hz to 10hz noise: 3.5v p-p n input bias current: 50pa maximum n low offset voltage: 1.25mv maximum n low offset drift: 5v/c maximum n cmrr: 130db minimum n rail-to-rail output stage n output sink and source: 50ma n 12mhz gain bandwidth product n 21v/s slew rate n 11nv/hz noise density n thermal shutdown n available in thermally enhanced soic-8e or tssop-16e packages n ate n piezo drivers n photodiode amplifier n high voltage regulators n optical networking high voltage dac buffer application v out = 70v 6090 ta01a ? + ltc6090 453k 10pf 70v 3v ?70v 16.2k 10k 470pf 16.9k v ref 2.5v ltc2641 d in 16 25s/div 80 60 40 20 0 ?20 ?40 ?60 ?80 6090 ta01b output voltage (v) l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltc6090/ltc6090-5 6090fd
2 for more information www.linear.com/ltc6090 p in c on f igura t ion a bsolu t e maxi m u m r a t ings total supply voltage (v + to v C ) ............................... 150 v c om ................................................................... v C to v + input voltage od ...................................................... v C to v + + 0.3 v + in , C in , .................................. v C C 0.3 v to v + + 0.3 v od to c om .................................................. C3 v to 7v input current + in , C in ........................................................... 1 0 ma tflag output tflag ...................................... v C C 0.3 v to v + + 0.3 v tflag to com ............................................ C3 v to 7v (note 1) 1 2 3 4 8 7 6 5 top view 9 v ? od v + out tflag com ?in +in v ? s8e package 8-lead plastic so t jmax = 150c, jc = 5c/w exposed pad ( pin 9) is v C , must be soldered to pcb fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 com guard guard ?in +in guard guard v ? 17 v ? od guard v + guard out guard guard tflag t jmax = 150c, jc = 10c/w exposed pad ( pin 17) is v C , must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description junction temperature range ltc6090cs8e#pbf ltc6090cs8e#trpbf 6090 8-lead plastic so 0c to 70c ltc6090is8e#pbf ltc6090is8e#trpbf 6090 8-lead plastic so C40c to 85c ltc6090hs8e#pbf ltc6090hs8e#trpbf 6090 8-lead plastic so C40c to 125c ltc6090cfe#pbf ltc6090cfe#trpbf 6090fe 16-lead plastic tssop 0c to 70c ltc6090ife#pbf ltc6090ife#trpbf 6090fe 16-lead plastic tssop C40c to 85c ltc6090hfe#pbf ltc6090hfe#trpbf 6090fe 16-lead plastic tssop C40c to 125c output current continuous ( no t e 2) .................................... 50 ma rms operating junction temperature range ( note 3) ................................................... C 40 c to 125 c specified junction temperature range ( note 4) ltc 6090 c ................................................ 0 c to 70 c ltc 609 0 i ............................................. C 40 c to 85 c ltc 609 0 h .......................................... C 40 c to 125 c junction temperature ( note 5) ............................. 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c ltc6090/ltc6090-5 6090fd
3 for more information www.linear.com/ltc6090 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications and all typical values are at t j = 25c. test conditions are v + = 70v, v C = C70v, v cm = v out = 0v, v od = open unless otherwise noted. o r d er i n f or m a t ion c-, i-suffixes h-suffix symbol parameter conditions min typ max min typ max units v os input offset voltage l 330 330 1000 1250 330 330 1000 1250 v v ?v os /?t input offset voltage drift t a = 25c, ?t j = 70c C5 3 5 C5 3 5 v/c i b input bias current (note 6) supply voltage = 70v supply voltage = 15v supply voltage = 15v l 3 0.3 50 3 0.3 800 pa pa pa i os input offset current (note 6) supply voltage = 15v l 0.5 30 0.5 120 pa pa e n input noise voltage density f = 1khz f = 10khz 14 11 14 11 nv / hz nv/hz input noise v oltage 0.1hz to 10hz 3.5 3.5 v p-p i n input noise current density 1 1 fa/hz v cm input common mode range guaranteed by cmrr l v C + 3v 68 v + C 3v v C + 3v 68 v + C 3v v v c in common mode input capacitance 9 9 pf c diff differential input capacitance 5 5 pf cmrr common mode rejection ratio v cm = C67v to 67v l 130 126 >140 130 126 >140 db db psrr power supply rejection ratio v s = 4.75v to 70v l 112 106 >120 112 106 >120 db db v out output voltage swing high ( v oh ) (referred to v + ) no load i source = 1ma i source = 10ma l l l 10 50 450 25 140 1000 10 50 450 25 140 1000 mv mv mv output v oltage swing low ( v ol ) (referred to v C ) no load i sink = 1ma i sink = 10ma l l l 10 40 250 25 80 600 10 40 250 25 80 600 mv mv mv a vol large-signal voltage gain r l = 10k, v out from C60v to 60v l 1000 1000 >10000 1000 1000 >10000 v /mv v/mv lead free finish tape and reel part marking* package description junction temperature range ltc6090cs8e-5#pbf ltc6090cs8e-5#trpbf 60905 8-lead plastic so 0c to 70c ltc6090is8e-5#pbf ltc6090is8e-5#trpbf 60905 8-lead plastic so C40c to 85c ltc6090hs8e-5#pbf ltc6090hs8e-5#trpbf 60905 8-lead plastic so C40c to 125c ltc6090cfe-5#pbf ltc6090cfe-5#trpbf 6090fe-5 16-lead plastic tssop 0c to 70c ltc6090ife-5#pbf ltc6090ife-5#trpbf 6090fe-5 16-lead plastic tssop C40c to 85c ltc6090hfe-5#pbf ltc6090hfe-5#trpbf 6090fe-5 16-lead plastic tssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc6090/ltc6090-5 6090fd
4 for more information www.linear.com/ltc6090 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications and all typical values are at t j = 25c. test conditions are v + = 70v, v C = C70v, v cm = v out = 0v, v od = open unless otherwise noted. c-, i-suffixes h-suffix symbol parameter conditions min typ max min typ max units i sc output short-circuit current (source and sink) supply v oltage = 70v supply voltage = 15v l 50 90 50 90 ma ma sr slew rate a v = C4, r l = 10k ltc6090 ltc6090-5 l l 10 18 21 37 9 16 21 37 v/s v/s gbw gain -bandwidth product f test = 20khz, r l = 10k ltc6090 ltc6090-5 l l 5.5 11 12 24 5 10 12 24 mhz mhz m phase margin r l = 10k, c l = 50pf 60 60 deg fpbw full power bandwidth v o = 125v pCp ltc6090 ltc6090-5 l l 20 34 40 68 18 32 40 68 khz khz t s settling time 0.1% ?v out = 1v ltc6090, a v = 1v/v ltc6090-5, a v = 5v/v 2 2.5 2 2.5 s s i s supply current no load l 2.8 3.9 4.3 2.8 3.9 4.3 ma ma v s supply voltage range guaranteed by the psrr test l 9.5 140 9.5 140 v od h od l od pin voltage, referenced to com pin v ih v il l l com + 1.8v com + 0.65 v com + 1.8v com + 0.65 v v v amplifier dc output impedance, disabled dc, od = com >10 >10 m com cm com pin voltage range l v C v + C 5 v C v + C 5 v com v com pin open circuit voltage l 17 21 25 17 21 25 v com r com pin resistance l 500 665 850 500 665 850 k temp f die temperature where tflag is active 145 145 c temp hys tflag output hysteresis 5 5 c i tflag tflag pull-down current tflag output voltage = 0v l 70 200 330 70 200 330 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6090/ ltc6090-5 is capable of producing peak output currents in excess of 50 ma. current density limitations within the ic require the continuous rms current supplied by the output ( sourcing or sinking) over the operating lifetime of the part be limited to under 50ma ( absolute maximum). proper heat sinking may be required to keep the junction temperature below the absolute maximum rating. refer to figure 7, the power dissipation section, and the safe operating area section of the data sheet for more information. note 3: the ltc6090c/ltc6090i are guaranteed functional over the operating junction temperature range C40c to 85c. the ltc6090h is guaranteed functional over the operating junction temperature range C40c to 125 c. specifying the junction temperature range as an operating condition is applicable for devices with potentially significant quiescent power dissipation. note 4: the ltc6090c is guaranteed to meet specified performance from 0c to 70c. the ltc6090c is designed, characterized, and expected to meet specified performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6090i is guaranteed to meet specified performance from C40c to 85c. the ltc6090h is guaranteed to meet specified performance from C40c to 125c. note 5: this device includes over temperature protection that is intended to protect the device during momentary overload conditions. operation above the specified maximum operating junction temperature is not recommended. note 6: input bias and offset current is production tested with 15v supplies. see typical performance characteristics curves of actual typical performance over full supply range. ltc6090/ltc6090-5 6090fd
5 for more information www.linear.com/ltc6090 typical p er f or m ance c harac t eris t ics frequency (khz) cmrr (db) 6090 g02 120 80 0 20 40 60 100 0.1 1000 10 1 100 v s = 70v ltc6090-5 ltc6090 ltc6090 ltc6090 ltc6090-5 ltc6090-5 frequency (khz) psrr (db) 6090 g03 140 120 60 0 20 40 100 80 0.1 1000 10 1 100 psrr? psrr+ a v = 1v/v frequency (khz) gain (db) phase (deg) 6090 g01 120 100 40 ?20 14 0 20 80 60 100 40 ?40 ?20 0 20 80 60 0.1 10000 100 101 1000 phase gain ltc6090-5 ltc6090 tcv os (v/c) number of units 6090 g05 350 200 0 50 100 150 300 250 ?6 ?4 20?2 64 v s = 70v t a = 25c ?t j = 70c v cm = 0v input common mode voltage (v) change in offset voltage (v) 6090 g06 20 ?20 ?10 0 10 ?75 0?25?50 755025 specified common mode range= 67v v s = 70v 125c 85c 25c ?50c temperature (c) ?50 ?500 voltage offset (v) ?400 ?200 ?100 0 500 200 0 50 75 100 6090 g07 ?300 300 400 100 ?25 25 125 v s = 70v v cm = 0v 5 samples total supply voltage (v) 5 ?500 offset voltage (v) ?300 ?100 100 30 55 80 105 6090 g08 130 300 500 ?400 ?200 0 200 400 t a = 25c 5 samples v + = ? v ? v cm = 0v total supply voltage (v) 5 change in offset voltage (v) ?25 0 25 8 10 6090 g09 ?50 ?75 ?100 6 7 9 50 75 100 125c 85c 25c ?50c v os (v) number of units 6090 g04 200 120 100 0 20 40 80 60 180 160 140 ?1000 1000 500 0 ?500 v s = 70v t a = 25c v cm = 0v open loop gain and phase vs frequency cmrr vs frequency psrr vs frequency v os distribution tcv os distribution change in offset voltage vs input common mode voltage offset voltage vs temperature offset voltage vs total supply voltage minimum supply voltage ltc6090/ltc6090-5 6090fd
6 for more information www.linear.com/ltc6090 typical p er f or m ance c harac t eris t ics frequency (khz) 10 voltage noise density (nv/ hz) 100 0.001 0.1 1 100 10 6090 g13 1 0.010 1000 frequency (khz) 10 0 integrated noise (v rms ) 150 200 250 100 1000 10000 6090 g14 100 50 frequency (khz) gain (db) 6090 g15 20 ?5 5 0 15 10 1 10000 1000 100 10 ltc6090 ltc6090-5 r f = 40.2k r i = 10k c f = 2pf frequency (khz) gain (db) 6090 g16 25 20 ?10 5 0 ?5 15 10 1 10000 1000 100 10 r f = 40.2k r i = 10k c f = 2pf c f = 1pf c f = 0pf frequency (khz) 0 gain (db) 20 40 50 1 100 1000 10000 6090 g17 ?20 10 30 10 ?10 av = 101v/v av = 11v/v av = 1v/v frequency (khz) gain (db) 6090 g18 50 ?10 40 20 10 30 0 1 10000 1000 100 10 5v/v 11v/v 33v/v 101v/v temperature (c) ?50 supply current (ma) 2.8 2.9 3.0 25 75 6090 g10 2.7 2.6 ?25 0 50 100 125 2.5 2.4 v s = 70v v s = 4.75v supply voltage (v) 0 0 supply current (ma) 0.5 1.0 1.5 2.0 3.0 25 50 75 100 6090 g11 125 150 2.5 t a = 25c total supply voltage (v) 0 output disable current (a) 400 6090 g12 200 0 50 100 25 75 125 600 800 300 100 500 700 125c 85c 25c ?50c integrated noise vs frequency small signal frequency response ltc6090-5 small signal frequency response vs feedback capacitance ltc6090 small signal frequency response vs closed loop gain ltc6090-5 small signal frequency response vs closed loop gain voltage noise density vs frequency supply current vs temperature supply current vs total supply voltage output disable supply current vs total supply voltage ltc6090/ltc6090-5 6090fd
7 for more information www.linear.com/ltc6090 typical p er f or m ance c harac t eris t ics frequency (khz) 0.1 output impedacne () 1 10 100 1000 1 100 1000 100000 6090 g19 0.01 10 10000 av = 101v/v av = 11v/v av = 1v/v frequency (khz) 1 1 output impedance (k) 10 100 1000 10 100 6091 g20 1000 c l = 10pf common mode voltage (v) 10 input bias current (|pa|) 100 ?80 0 40 6090 g21 1 ?40?60 20 60 ?20 80 125c v s = 70v 100c 80c 50c direction of the current is out of the pin 25c 5c 0.1 1000 10000 common mode voltage (v) 1 input bias current (|pa|) 100 1000 ?15 5 15 6090 g22 0.1 ?5?10 10 0 10 125c 100c v s = 15v 50c 25c 85c direction of the current is out of the pin output, input (v) 0 20 40 6090 g23 ?20 ?40 ?80 5s/div ?60 80 60 input output a v = ?10v/v v s = 70v output, input (v) 0 20 40 6090 g24 ?20 ?40 ?80 5s/div ?60 80 60 input output a v = ?10v/v v s = 70v r f = 100k r i = 10k c f = 2pf input 50mv/div output 50mv/div 6090 g16 1s/div a v = 1v/v input step (0.5v/div) output step (20mv/div) 500ns/div 6090 g26 a v = 1v/v input output input step (0.5v/div) output step (20mv/div) 500ns/div 6090 g27 a v = 1v/v input output ltc6090-5 large signal transient response small signal transient response ltc6090 falling edge settling time ltc6090 rising edge settling time input bias current vs common mode voltage and temperature input bias current vs common mode voltage and temperature ltc6090 large signal transient response output impedance vs frequency output impedance vs frequency with output disabled (od = com) ltc6090/ltc6090-5 6090fd
8 for more information www.linear.com/ltc6090 typical p er f or m ance c harac t eris t ics 0.1hz to 10hz voltage noise supply current vs od pin voltage od pin input current vs od pin voltage output voltage swing high (v oh ) vs load current and temperature ltc6090-5 falling edge settling time output disable (od) response time output voltage swing vs frequency ltc6090-5 small signal transient response ltc6090-5 rising edge settling time 1s/div input 25mv/div output 100mv/div 6090 g28 a v = 5v/v r f = 40.2k r i = 10k c f = 2pf 500ns/div input (100mv/div) output (50mv/div) 6090 g29 a v = 5v/v r f = 40.2k r i = 10k c f = 2pf input output 500ns/div input (100mv/div) output (50mv/div) 6090 g30 input output a v = 5v/v r f = 40.2k r i = 10k c f = 2pf 6090 g31 20s/div od-com od-com = 0v 2v/div output enabled output disabled v out = 0v a v = ?10v/v v in = ?0.5v v out frequency (khz) v out (v p-p ) 6090 g32 160 0 140 100 80 60 40 120 20 1 1000 100 10 ltc6090-5 ltc6090 a v = ?10v/v v s = 70v r f = 100k r i = 10k c f = 2pf time (1s/div) output noise 2v/div 6090 g33 od-com (v) 0.5 0 supply current (ma) 0.5 1.0 1.5 2.0 3.0 0.8 1.0 1.3 1.5 6090 g34 1.8 2.0 2.5 125c 85c 25c ?50c v s = 70v v com = 0v od-com (v) 0 1 ?50 od input current (a) 0 ?25 2 6 75 50 25 3 4 5 7 6090 g35 125c 85c 25c ?50c v s = 70v v com = 0v i source (ma) 0 v oh (mv) 300 400 500 6 10 6090 g36 200 100 0 2 4 8 600 700 800 125c 85c 25c ?50c ltc6090/ltc6090-5 6090fd
9 for more information www.linear.com/ltc6090 typical p er f or m ance c harac t eris t ics output voltage swing low (v ol ) vs load current and temperature open circuit voltage of com, od, tflag ltc6090 distortion vs frequency open loop gain thermal shutdown hysteresis open loop gain vs load resistance i source (ma) 0 v ol (mv) 150 200 250 6 10 6090 g37 100 50 0 2 4 8 300 400 350 500 450 125c 85c 25c ?50c frequency (khz) distortion (dbc) 6090 g38 ?20 ?120 ?110 ?100 ?90 ?50 ?40 ?30 ?80 ?70 ?60 10 100 v s = 70v a v = 10 v out = 10v p-p r l = 10k 2nd 3rd junction temperature (c) supply current (ma) 6090 g39 3.0 0 0.5 1.0 2.5 2.0 1.5 162 178 170 166164 168 176174172 total supply voltage (v) pin voltage (v) 6090 g40 100 0 20 40 80 60 0 140 80 4020 60 120100 od com tflag v ? = 0v output voltage (v) change in voltage offset (v) 6090 g41 40 ?40 ?30 10 20 30 ?20 ?10 0 ?70 ?50 ?25 0 25 50 75 v s = 70v r load = 10k t a = 25c 10 samples output voltage (v) change in voltage offset (v) 6090 g42 40 ?40 ?30 10 20 30 ?20 ?10 0 ?70 ?50 ?25 0 25 50 75 r load = 100k r load = 10k r load = 500k ltc6090/ltc6090-5 6090fd
10 for more information www.linear.com/ltc6090 p in func t ions com (pin 1/pin 1): com pin is used to interface od and tflag pins to voltage control circuits. tie this pin to the low voltage ground, or let it float. Cin (pin 2/pin 4): inverting input pin. input common mode range is v C + 3 v to v + C 3 v. do not exceed absolute maximum voltage range. +in (pin 3/pin 5): noninverting input pin. input common mode range is v C + 3 v to v + C 3 v. do not exceed absolute maximum voltage range. v C (pin 4, exposed pad pin 9/pin 8, exposed pad pin 17): negative supply pin. connect to v C only. to achieve low thermal resistance connect this pin to the v C power plane. the v C power plane connection removes heat from the device and should be electrically isolated from all other power planes. tflag (pins 5, 9/pins 9, 17): temperature flag pin. the tflag pin is an open drain output that sinks current when the die temperature exceeds 145c. out (pin 6/pin 12): output pin. if this rail-to-rail output goes below v C , the esd protection diode will forward bias. if out goes above v + , then output device diodes will forward bias. avoid forward biasing the diodes on the out pin. excessive current can cause damage. v + (pin 7/pin 14): positive supply pin. od (pin 8/pin 16): output disable pin. active low input disables the output stage. if left open, an internal pull-up resistor enables the amplifier. input voltage levels are referred to the com pin. guard (na/pins 2, 3, 6, 7, 10, 11, 13, 15): guard pins increase clearance and creepage between other pins. pins 3 and 6 can be used to build guard rings around the inputs. (s8e/fe) ltc6090/ltc6090-5 6090fd
11 for more information www.linear.com/ltc6090 b lock diagra m 6090 bd t j > 175c t j > 145c ? + v + 10k 2m v + 2m com ?in +in v ? v ? 2m 10k v ? differential drive generator output enable 500 v ? v ? v ? 6k to com pin 6k die temperature sensor input stage v + 125 125 od tflag v + out v ? esd esd esd esd esd esd 1.2v ltc6090/ltc6090-5 6090fd
12 for more information www.linear.com/ltc6090 general the ltc6090 high voltage operational amplifier is designed in a linear technology proprietary process enabling a rail- to-rail output stage with a 140 v supply while maintaining precision, low offset, and low noise. power supply the ltc6090 works off single or split supplies. split sup - plies can be balanced or unbalanced. for example, two 70v supplies can be used, or a 100 v and C40 v supply can be used. for single supply applications place a high quality surface mount ceramic 0.1 f bypass capacitor between the supply pins close to the part. for dual supply applications use two high quality surface mount ceramic capacitors between v + to ground, and v C to ground located close to the part. when using split supplies, supply se- quencing does not cause problems. input protection as shown in the block diagram, the ltc6090 has a com - prehensive protection network to prevent damage to the input devices. the current limiting resistors and back to back diodes are to keep the inputs from being driven apart. the voltage-current relationship combines exponential and resistive until the voltage difference between the pins reach 12v. at that point the zeners turn on. additional current into the pins will snap back the input differential voltage to 9v. in the event of an esd strike between an input and v C , the voltage clamps and esd device fire providing a current path to v C protecting the input devices. the input pin protection is designed to protect against momentary esd events. a repetitive large fast input swing (>5.5v and <20 ns rise time) will cause repeated stress on the mosfet input devices. when in such an application, anti- parallel diodes (1n 4148) should be connected between the inputs to limit the swing. feedback resistor selection to get the most accuracy, the feedback resistor should be chosen carefully. consider an amplifier with a v = C50 and a 5 k feedback resistor. a 1 v input will cause the output to figure 1. low voltage interface a pplica t ions i n f or m a t ion rise to 50 v, causing 10 ma to flow through the feedback resistor. the power dissipated in the output stage will create thermal feedback to the input stage potentially causing shifts in offset voltage. a better choice is a 50k feedback resistor reducing the current in the feedback resistor to 1ma. interfacing to low voltage circuits the com pin is provided to set a common signal ground for communication to a microprocessor or other low volt- age logic circuit. the com pin should be tied to the low voltage ground as shown in figure 1. if left floating, the internal resistive voltage divider will cause the com pin to rise 30% above mid-supply. the com, od , and tflag pins are protected from overvoltage by internal zener diodes and current limiting resistors. extra care should be taken to observe the absolute maximum voltage limits between (od and com) and between (tflag and com). voltage limits between these pins must remain between C3v and 7v. 6090 f01 od com ltc6090 tflag 10k low voltage supply tie to low voltage ground to low voltage control to low voltage control 6k 200k v + v ? v ? 2m v + 2m 2m 10k 6k 500 ltc6090/ltc6090-5 6090fd
13 for more information www.linear.com/ltc6090 a pplica t ions i n f or m a t ion figure 2. starting up figure 3. ltc6090 output disable function 1ms/div 6090 f02 out 10v/div v+ 2.5ms/div 6090 f03 out 2v/div od 2v/div output disable the od pin is an active low disable with an internal 2m resistor that will pull up the od pin enabling the output stage if left open. the od pin voltage is limited by an internal zener diode. when the od pin is brought low to within 0.65 v of the com pin, the output stage is disabled, leaving the bias and input circuits enabled. this results in 580a ( typical) standby current through the device. the od pin can be directly connected to the low voltage logic or an open drain nmos device as shown in figure 1. for simplest shutdown operation, float the com pin, and tie the od pin to the tflag pin. this will float the low voltage control pins, and the overtemperature circuit will safely shutdown the output stage if the die temperature reaches 145c. extra care should be taken to observe the absolute maxi - mum voltage limits between (od and com) and between (tflag and com). voltage limits between these pins must remain between C3v and 7v. when coming out of shutdown the ltc6090 bias circuits and input stage are already powered up leaving only the output stage to turn on and drive to the proper output voltage. figures 2 and 3 show the part starting up and coming out of shutdown, respectively. thermal shutdown the tflag pin is an open drain output pin that sinks 200a (typical) when the die temperature exceeds 145 c. the temperature sensor has 5 c of hysteresis requiring the part to cool to 140 c before disabling the tflag pin. extra care should be taken to observe the absolute maximum voltage limits between ( od and com) and between ( tflag and com). voltage limits between these pins must remain between C3v and 7v. tying the the tflag pin to the od pin will automatically shut down the output stage as shown in figure 4. this will ensure the junction temperature does not exceed 150c. for safety, an independent second overtemperature threshold shuts down the output stage if the internal die temperature rises to 175 c. there is hysteresis in the thermal shutdown circuit requiring the die temperature to cool 7 c. once the device has cooled sufficiently, the output stage will enable. degradation can occur or reli - ability may be affected when the junction temperature of the device exceeds 150c. figure 4. automatic thermal output disable using the tflag pin 6090 f04 od tflag 10k com optional (can be left floating) 6k v + v ? 2m ltc6090 ltc6090/ltc6090-5 6090fd
14 for more information www.linear.com/ltc6090 a pplica t ions i n f or m a t ion board layout the ltc6090 is a precision low offset high gain ampli- fier that requires good analog pcb layout techniques to maintain high performance. start with a ground plane that is star connected. pull back the ground plane from any high voltage vias. critical signals such as the inputs should have short and narrow pcb traces to reduce stray capacitance which also improves stability. use high quality surface mount ceramic capacitors to bypass the supply (s ). in addition to the typical layout issues encountered with a precision operational amplifier, there are the issues of high voltage and high power. important consideration for high voltage traces are spacing, humidity and dust. high voltage electric fields between adjacent conductors attract dust. moisture is absorbed by the dust and can contribute to board leakage and electrical breakdown. it is important to clean the pcb after soldering down the part. solder flux will accumulate dust and become a leak- age hazard. it is recommended to clean the pcb with a solvent, or simply use soap and water to remove residue. baking the pcb will remove left over moisture. depending on the application, a special low leakage board material may be considered. the tssop package has guard pins for applications that require a guard ring. an example schematic diagram and pcb layout is shown in figures 5 a and 5 b, respectively, of a circuit using a guard ring to protect the C in pin. the guard ring completely encloses the high impedance node Cin. to simplify the pcb layout avoid using vias on this node. in addition, the solder mask should be pulled back along the guard ring exposing the metal. to help the spacing between nodes, one of the extra pins on the tssop package is used to route the guard ring behind the Cin pin. the pcb should be thoroughly cleaned after soldering to ensure there is no solder paste between the exposed pad (pin 17) and the guard ring. 6090 f05a ? + ltc6090 r2 c2 r1 guard ring figure 5a. circuit diagram showing guard ring figure 5b. tssop package pcb layout with guard ring 6090 f05b r2 c2 r1 ?in +in out ltc6090/ltc6090-5 6090fd
15 for more information www.linear.com/ltc6090 a pplica t ions i n f or m a t ion power dissipation with a supply voltage of 140 v it doesnt take much current to consume a lot of power. consider that 10 ma at 140v consumes 1.4 w of power and needs to be dissipated in a small plastic so package. to aid in power dissipation both ltc6090 packages have exposed pads for low thermal resistance. the amount of metal connected to the exposed pad will lower the ja of a package. an optimal amount of pcb metal connected to the so package will lower the junction to ambient thermal resistance down to 33c/w. if minimal metal is used, the ja could more than double (see table 1). if the exposed pad has no metal beneath it, ja could be as high 120c/w. its recommended that the exposed pad have as much pcb metal connected to it as reasonably available. the more pcb top layer a top layer b top layer c top layer d example a example b example c example d bottom layer a ja = 43c/w jc = 5c/w ca = 38c/w ja = 50c/w jc = 5c/w ca = 45c/w ja = 57c/w jc = 5c/w ca = 52c/w ja = 54c/w jc = 5c/w ca = 49c/w ja = 57c/w jc = 5c/w ca = 52c/w ja = 58c/w jc = 5c/w ca = 53c/w ja = 72c/w jc = 5c/w ca = 67c/w bottom layer b bottom layer c minimum bottom layer a minimum bottom layer b minimum bottom layer c bottom layer d table 1. thermal resistance as pcb area of exposed pad varies metal connected to the exposed pad, the lower the thermal resistance. use multiple vias from the exposed pad to the v C supply plane. the exposed pad is electrically connected to the v C pin. in addition, a heat sink may be necessary if operating near maximum junction temperature. see table 1 for guidance on how thermal resistance changes as a function of metal area connected to the exposed pad. the ltc6090 is specified to source and sink 10ma at 140v. if the total supply voltage is dropped across the device, 1.4w of power will need to be dissipated. if the quiescent power is included (140v ? 2.8ma = 0.4 w), the total power dissipated is 1.8w. the internal die temperature will rise 59 using an optimal layout in a so package. a sub- optimal layout could more than double the amount of temperature increase due to power dissipation. ltc6090/ltc6090-5 6090fd
16 for more information www.linear.com/ltc6090 a pplica t ions i n f or m a t ion in order to avoid damaging the device, the absolute maximum junction temperature should not be exceeded (t jmax = 150 c). junction temperature is determined using the expression: t j = pd ? ja + t a where p d is the power dissipated in the package, ja is the package thermal resistance from ambient to junction and t a is the ambient temperature. for example, if the part has a 140 v supply voltage with 2.8 ma of quiescent current and the output is 20 v above the negative rail sourcing 10ma, the total power dissipated in the device is (120 v ? 10ma ) + (140v ? 2.8ma ) = 1.6 w. under these conditions the ambient temperature should not exceed: t a = t jmax C (p d ? ja ) = 150c C (1.6w ? 33c/w) = 97c. safe operating area the safe operating area, or soa, illustrates the voltage, current, and temperature conditions where the device can be reliably operated. shown below in figure 6 is the soa for the ltc6090. the soa takes into account ambient temperature and the power dissipated by the device. this includes the product of the load current and difference between the supply and output voltage, and the quiescent current and supply voltage. the ltc6090 is safe when operated within the boundaries shown in figure 6. thermal resistance junction to case, jc , is rated at a constant 5 c/w. thermal resistance junction to ambient, ja , is dependent on board layout figure 8. closed loop response with various feedback capacitors figure 7. ltc6090 with feedback capacitance to reduce peaking figure 6. safe operating area 6090 f07 ? + ltc6090 100k c f 10k parasitic input capacitance junction temperature limited supply voltage ? load voltage (v) load current (ma) 6090 f06 100 10 1 10 1 1000 100 current density limited ja = 33c/w ja = 60c/w ja = 100c/w ja = 33c/w ja = 60c/w ja = 100c/w t a = 25c t a = 90c frequency (khz) gain (db) 6090 f08 25 20 15 10 1 1000 100 10 c f = 4pf c f = 2pf c f = 0pf and any additional heat sinking. the six soa curves in figure 6 show the direct effect of ja on soa. stability with large resistor values a large feedback resistor along with the intrinsic input capacitance will create an additional pole that affects stability and causes peaking in the closed loop response. to mitigate the peaking a small feedback capacitor placed around the feedback resistor, as shown in figure 7, will reduce the peaking and overshoot. figure 8 shows the closed loop response with various feedback capacitors. additionally stray capacitance on the input pins should be kept to a minimum. with pa input current, the pcb traces should be routed as short and narrow as possible. ltc6090/ltc6090-5 6090fd
17 for more information www.linear.com/ltc6090 a pplica t ions i n f or m a t ion slew enhancement the ltc6090 includes a slew enhancement circuit which boosts the slew rate to 21 v/s making the part capable of slewing rail-to-rail across the 140 v output range in less than 7s. to optimize the slew rate and minimize settling, stray capacitance should be kept to a minimum. a feedback capacitor reduces overshoot and nonlinearities associated with the slew enhancement circuit. the size of the feedback capacitor should be tailored to the specific board, supply voltage and load conditions. slewing is a nonlinear behavior and will affect distortion. the relationship between slew rate and full power band - width is given in the relationship below. sr = v o ? where v o is the peak output voltage and is frequency in radians. the fidelity of a large sine wave output is limited by the slew rate. the graph in figure 9 shows distortion versus frequency for several output levels. multiplexer application several ltc6090s may be arranged to act as a high volt - age analog multiplexer as shown in figure 10. when using this arrangement, it is possible for the output to affect the source on the disabled amplifiers noninverting input. the inverting and noninverting inputs are clamped through resistors and back to back diodes. there is a path for current to flow from the multiplexer output through the disabled amplifiers feedback resistor, and through the inputs to the noninverting inputs source. for example, if the enabled amplifier has a C70 v output, and the disabled amplifier has a 5 v input, there is 75 v across the two resis - tors and the input pins. to keep this current below 1ma the combined resistance of the r in and feedback resistor needs to be about 75k. the output impedance of the disabled amplifier is greater than 10 m at dc. the ac output impedance is shown in the typical performance characteristics section. figure 10. multiplexer application figure 9. distortion vs frequency for large output swings frequency (hz) total harmonic distortion + noise (%) 6090 f09 10 0.1 1 0.01 0.001 10 100000 100 1000 10000 v s = 70v a v = 5 r l = 10k c f = 30pf v out = 100v p-p v out = 50v p-p v out = 10v p-p 6090 f10 ch1 10k od od 10k 10k 100k 10k 100k ch2 select ? + ? + ltc6090 ltc6090 com mux out com ltc6090/ltc6090-5 6090fd
18 for more information www.linear.com/ltc6090 typical a pplica t ions gain of 20 amplifier with a 40ma protected output driver gain of 10 with protected output current doubler 12v to 70v isolated flyback converter for amplifier supply 6090 ta04 lt3511 v in v in 12v v c gnd bias r fb r ref sw t c 2.2nf 24.9k 10k bav20w bzx100a en/uvlo 4.7f 100k 1m 562k ? crm1u-06m crm1u-06m 0.47f 100v 0.47f 100v 2.2f v out1 + v out2 ? + ? ltc6090 70v ?70v ? ? 750311692 1:1:5 6090 ta05 v in 9v 100k 22k ? cmmr1u-2 750311692 1:1:5 cmmr1u-2 cmhz5266b 1f 100v 1f 130v + ? ltc6090 65v ?65v ? ? 5 4 1 2 3 4.7f 4 3 130k en/uvlo gnd r fb v in sw lt8300 8 6 7 5 9v to 65v isolated flyback converter for amplifier supply 6090 ta03 ? + ltc6090 70v ?70v 200k 1% 200k tf od 22.1k 1% v in 100 1% ? + ltc6090 70v ?70v tf od 100 1% 70v at 20ma 6090 ta02 ? + 604 6 8 1 5 7 4 2 3 9 47pf bav99 bav99 ltc6090 70v ?70v 12.1 40.2k tf od v out czt5401 1k 1k czt5551 2k 2k40.2k v in ltc6090/ltc6090-5 6090fd
19 for more information www.linear.com/ltc6090 typical a pplica t ions audio power amplifier frequency (hz) total harmonic distortion plus noise (%) 6090 ta06b 0.100 0 0.001 0.010 10 100 100000 10000 1000 8 at 50w 4 at 100w total harmonic distortion plus noise analyzer passband 10hz to 80khz lt1166 v top sense+ v bottom sense? v in v out i lim + 100k 1k 100pf i lim ? ? + ltc6090 100pf 100k 10 1k 0.1 ixth50n20 ixth24p20 6090 ta06a out 0.1 33.2k 40.2 1nf 2.49k 1k czt5551 1n4148 czt5401 1n4148 * use several series resistors to reduce distortion (i.e. 5 2k). 33.2k 10k* 1nf 100pf 1n4148 1n4148 39.2 20k in 499 4 499 1nf 9 1 7 5 8 6 2 3 ?50v 50v 100pf 1k 1f 1f 1n4148 1n4148 22nf 1h ltc6090/ltc6090-5 6090fd
20 for more information www.linear.com/ltc6090 typical a pplica t ions high current pulse amplifier 60v step response into 10? 5s/div volts 6090 ta07b 10 20 30 ?20 ?10 0 40 ? + ltc6090 6090 ta07 out 499k 499 10k in 4 9 1 7 5 6 8 2 3 499 ?70v 70v 2sk1057 2sj161 10k 75pf 1k 100 ihsm-3825 1h ltc6090/ltc6090-5 6090fd
21 for more information www.linear.com/ltc6090 ? + ltc6090 6090 ta08a out 499k 10k in 4 9 6 1 7 5 8 2 3 100 100nf 100nf 499 ?50v 50v 2sk1057 2sj161 2sj161 2k 2k 2k 50pf 2k 2k ihsm-3825 1h 2sk1057 100 set quiescent supply current at about 200ma with bias adjustment. set quiescent current to 100ma if parallel mosfets are not used (for 8 or higher). 100k 100k 6.8k bias 10k 6.8k 1k 1k frequency (hz) total harmonic distortion plus noise (%) 6090 ta08b 1 0.0001 0.001 0.01 0.1 10k 1k 100 8 at 50w 4 at 100w typical a pplica t ions simple 100w audio amplifier total harmonic distortion plus noise vs frequency ltc6090/ltc6090-5 6090fd
22 for more information www.linear.com/ltc6090 typical a pplica t ions wide common mode range 10x gain instrumentation amplifier typically <1mv input-referred error + ? ltc6090 205k 10k* 22pf 4 9 6 1 7 5 8 3 2 + ? ltc6090 4 9 6 1 7 5 8 3 2 24.9k 100k 100k ?70v 70v ?70v 70v * these resistors can be 0 if input signal source impedances are <20m. 22pf 10k* + ? ltc6090 100k lt5400-2 100k 100k 100k 4 9 6 1 7 5 8 3 2 1 2 3 4 8 7 6 5 9 22pf 22pf +in ?in 70v ?70v ltc6090 ta09 49.9 out ?3db at 45khz cm frequency (khz) cmrr (db) 6090 ta09b 90 40 50 60 70 80 1 10 100 ltc6090/ltc6090-5 6090fd
23 for more information www.linear.com/ltc6090 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe16 (ba) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 10 9 4.90 ? 5.10* (.193 ? .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 ? 0.30 (.0077 ? .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation ba ltc6090/ltc6090-5 6090fd
24 for more information www.linear.com/ltc6090 p ackage descrip t ion .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) s8e 1013 rev a .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .080 ? .098 (2.032 ? 2.489) .118 ? .138 (2.997 ? 3.505) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 .005 (0.13) max 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .160 .005 (4.06 0.127) .118 (2.99) ref recommended solder pad layout .045 .005 (1.143 0.127) .050 (1.27) bsc inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8e package 8-lead plastic soic (narrow .150 inch) exposed pad (reference ltc dwg # 05-08-1857 rev a) .089 (2.26) ref .030 .005 (0.76 0.127) typ .245 (6.22) min please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc6090/ltc6090-5 6090fd
25 for more information www.linear.com/ltc6090 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 11/12 added esd statement. 2 b 9/13 corrected schematics 16, 17, 18 c 6/14 added ltc6090-5, improved specs. all d 5/15 removed esd statement to reflect improved esd performance. changed internal tflag circuit resistor values. updated thermal shutdown description. corrected application circuit resistor value. 2 11, 12 13 19, 20, 21 ltc6090/ltc6090-5 6090fd
26 for more information www.linear.com/ltc6090 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2012 lt 0515 rev d ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc6090 r ela t e d p ar t s typical a pplica t ion part number description comments amplifiers lt1990 250v input range g = 1, 10, micropower, difference amplifier pin selectable gain of 1 or 10 lt1991 precision, 100a gain selectable amplifier pin configurable as a difference amplifier, inverting and noninverting amplifier matched resistors lt5400 quad matched resistor network excellent matching specifications over the entire temperature range digital to analog converters ltc2641/ltc2642 16-bit v out dacs in 3mm 3mm dfn guaranteed monotonic over temperature ltc2756 serial 18-bit softspan i out dac 18-bit settling time: 2.1s maximum 18-bit inl error: 1 lsb over temperature flyback controllers lt3511 monolithic high v oltage isolated flyback converter 4.5v to 100v input voltage range, no opto-coupler required lt8300 100v in micropower isolated flyback converter with 150v/260ma switch 6v to 100v input voltage range. v out set with a single external resistor extended dynamic range 1m? transimpedance photodiode amplifier 6090 ta10 ? + 200k 1% 100mw 22.1k 1% 1 4 2 3 ltc6090 photodiode sfh213 125v 0.3pf ?3v ?3v 10m 1% v out v out = i pd ? 1m output noise = 21v rms (1khz ? 40khz) output offset = 150v maximum bandwidth = 40khz (?3db) output swing = 0v to 12v i pd 7 8 5 6 ltc6090/ltc6090-5 6090fd

▲Up To Search▲

Price & Availability of LTC6090-5-15

	To Download LTC6090-5-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .